While long polar codes can achieve the capacity of arbitrary binary-inputdiscrete memoryless channels when decoded by a low complexity successivecancelation (SC) algorithm, the error performance of the SC algorithm isinferior for polar codes with finite block lengths. The cyclic redundancy check(CRC) aided successive cancelation list (SCL) decoding algorithm has bettererror performance than the SC algorithm. However, current CRC aided SCL(CA-SCL) decoders still suffer from long decoding latency and limitedthroughput. In this paper, a reduced latency list decoding (RLLD) algorithm forpolar codes is proposed. Our RLLD algorithm performs the list decoding on abinary tree, whose leaves correspond to the bits of a polar code. In existingSCL decoding algorithms, all the nodes in the tree are traversed and allpossibilities of the information bits are considered. Instead, our RLLDalgorithm visits much fewer nodes in the tree and considers fewer possibilitiesof the information bits. When configured properly, our RLLD algorithmsignificantly reduces the decoding latency and hence improves throughput, whileintroducing little performance degradation. Based on our RLLD algorithm, wealso propose a high throughput list decoder architecture, which is suitable forlarger block lengths due to its scalable partial sum computation unit. Ourdecoder architecture has been implemented for different block lengths and listsizes using the TSMC 90nm CMOS technology. The implementation resultsdemonstrate that our decoders achieve significant latency reduction and areaefficiency improvement compared with other list polar decoders in theliterature.
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